1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of controlling exposure processes by monitoring photon levels, and a system for accomplishing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background, an illustrative field effect transistor 10, as shown in FIG. 1, may be formed above a surface 15 of a semiconducting substrate or wafer 11 comprised of doped-silicon. The substrate 11 may be doped with either N-type or P-type dopant materials. The transistor 10 may have a doped polycrystalline silicon (polysilicon) gate electrode 14 formed above a gate insulation layer 16. The gate electrode 14 and the gate insulation layer 16 may be separated from doped source/drain regions 22 of the transistor 10 by a dielectric sidewall spacer 20. The source/drain regions 22 for the transistor 10 may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate 11. Shallow trench isolation regions 18 may be provided to isolate the transistor 10 electrically from neighboring semiconductor devices, such as other transistors (not shown).
The gate electrode 14 has a critical dimension 12, i.e., the width of the gate electrode 14, that approximately corresponds to the channel length 13 of the device when the transistor 10 is operational. Of course, the critical dimension 12 of the gate electrode 14 is but one example of a feature that must be formed very accurately in modern semiconductor manufacturing operations. Other examples include, but are not limited to, conductive lines, openings in insulating layers to allow subsequent formation of a conductive interconnection, i.e., a conductive line or contact, therein, etc.
In the process of forming integrated circuit devices, millions of semiconductor devices, such as the illustrative transistor 10 depicted in FIG. 1, are formed above a semiconducting substrate. In general, semiconductor manufacturing operations involve, among other things, the formation of layers of various materials, e.g., polysilicon, metals, insulating materials, etc., and the selective removal of portions of those layers by performing known photolithographic and etching techniques. These processes are continued until such time as the integrated circuit device is complete. Additionally, although not depicted in FIG. 1, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate. These conductive interconnections allow electrical signals to propagate between the transistors formed above the substrate.
During the course of fabricating such integrated circuit devices, a variety of features, e.g., gate electrodes, conductive lines, openings in layers of insulating material, etc., are formed to very precisely controlled dimensions. Such dimensions are sometimes referred to as the critical dimension (CD) of the feature. It is very important in modern semiconductor processing that features be formed as accurately as possible due to the reduced size of those features in such modern devices. For example, gate electrodes may now be patterned to a width 12 that is approximately 0.18 μm (1800 Å), and further reductions are planned in the future. As stated previously, the width 12 of the gate electrode 14 corresponds approximately to the channel length 13 of the transistor 10 when it is operational. Thus, even slight variations in the actual dimension of the feature as fabricated may adversely affect device performance. Thus, there is a great desire for a method that may be used to accurately, reliably and repeatedly form features to their desired critical dimension, i.e., to form the gate electrode 14 to its desired critical dimension 12.
Photolithography is a process typically employed in semiconductor manufacturing. Photolithography generally involves forming a photo-sensitive layer, e.g., a layer of photo-resist material (positive or negative), above one or more layers of material, e.g., polysilicon, silicon dioxide, that are desired to be patterned. Thereafter, a pattern that is desired to be formed in the underlying layer or layers of material is initially formed in the photo-sensitive layer, e.g., the layer of photoresist, using an appropriate stepper tool or phase scanner tool and known photolithographic techniques, i.e., an image on a reticle in the stepper tool is transferred to the layer of photoresist by exposing the layer of photoresist with a light source, e.g., an ultraviolet or deep-ultraviolet (DUV) light source. Then, the exposed layer of photoresist is developed so as to leave in place a patterned layer of photoresist (or photo mask) substantially corresponding to the pattern on the reticle. This patterned layer of photoresist is then used as a mask in subsequent etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features or opening-type features, that are to be replicated in an underlying process layer. The features in the patterned layer of photoresist also have a critical dimension, sometimes referred to as a develop inspect critical dimension (DICD).
More particularly, in one illustrative embodiment, modern photolithography processes generally involve the steps of: (1) applying a layer of photoresist above a wafer, typically accomplished by a spin-coating process; (2) pre-baking (or soft-baking) the layer of photo-resist at a temperature of approximately 90–120° C. to reduce the level of solvents in the layer of photoresist and to improve the adhesion characteristics of the photoresist; (3) performing an exposure process, wherein the layer of photoresist is exposed to a light source and a pattern is projected onto the layer of photoresist through a reticle used in a stepper tool to create a latent image in the layer of photoresist; (4) performing a post-exposure bake on the layer of photoresist at a temperature approximately 5–15° C. higher than the pre-bake process; (5) performing a develop process to turn the latent image in the layer of photoresist into the final resist image; and (6) performing a post-bake process (or hard-bake) at a temperature of approximately 125–160° C. to remove residual solids, improve adhesion, and to increase the etch resistance of the photoresist. These process steps are well known to those skilled in the art and, thus, will not be described herein in any greater detail.
However, in the process of forming the layer of photoresist above a wafer, the thickness of the layer of photoresist may vary across the surface of the wafer (within wafer variations) as well as from wafer to wafer (wafer-to-wafer variations). These variations may be localized within a wafer, e.g., the photoresist material formed on an edge region of a wafer may be thicker than the photoresist material in a middle region of the wafer.
Such variations may be the result of a variety of factors. For example, the amount of photoresist initially deposited may vary, the wafer may be rotated at a speed greater or less than the desired rotational speed, the duration of the spinning process may be more or less than anticipated, and the viscosity of the photoresist material may vary as the photoresist material is consumed and replenished. Additionally, variations in cooling of the wafer prior to photoresist application and variations in the pre-exposure bake process may result in the layer of photoresist having unanticipated thickness variations.
In general, the exposure process is performed with parameters that are preselected based upon the anticipated condition of the incoming layer of photoresist, e.g., thickness, across-wafer uniformity, etc. That is, parameters, such as the exposure dose, are determined based upon anticipated conditions of the layer of photoresist, However, unanticipated variations in the layer of photoresist may adversely affect the ability to produce semiconductor devices having the desired feature size. For example, if the layer of photoresist is thicker than anticipated (either across the wafer or from wafer to wafer), a feature, e.g., a gate electrode, may be formed with a critical dimension greater than anticipated. The critical dimensions may also be smaller than anticipated, depending upon the critical dimension swing curve of the photolithography process. This situation may occur when the exposure process is performed with parameters, e.g., exposure dose, that are intended to be performed on a layer of photoresist having a lesser thickness. Conversely, if the layer of photoresist is thinner than anticipated, the resulting gate electrodes may have a critical dimension that is less than or greater than a targeted critical dimension. All of the identified problems tend to lead to inefficiencies in manufacturing operations and reduce product yields.
Moreover, in some cases, the light source used in the exposure process tends to degrade over time due to repetitive use. Such degradation may adversely impact the ability to expose the photo-sensitive layer in the desired manner. More specifically, performing an exposure process using a preselected exposure dose with a degraded light source may result in a less than satisfactory exposure process. Ultimately, such a situation may lead to reduced manufacturing efficiencies.
The present invention is directed to a method and system that may solve, or at least reduce, some or all of the aforementioned problems.